The increasing complexity of systems that can be integrated on a single integrated circuit (IC) die has lead to design methodologies that allow designers to design and verify a system at an abstract or block diagram level prior to development of the detailed design of the individual design blocks. The design methodology may involve mapping a system level algorithm to a particular architecture that is partitioned into design blocks that represent sections of a circuit to be simulated and verified. A typical top down design flow for a mixed-signal integrated system may involve several distinct phases such as, system design, architecture design, cell design, and cell-layout. The performance required of individual design blocks to meet overall system performance may be evaluated through simulation and verification before details of the design blocks are fully developed.
The simulation of a mixed-signal circuit that includes both digital and analog design blocks involves two methods of simulation: event-driven digital simulation as found in logic simulators and continuous-time analog simulation as found in circuit simulators. Digital design blocks encoded in computer readable storage devices are simulated using a digital simulator, and analog blocks encoded in computer readable storage devices are simulated using an analog circuit simulator. Digital simulation and analog simulation are fundamentally different. While a digital simulator solves expressions representing logical or functional behavior of a circuit based upon the occurrence of discrete triggering events, an analog simulator solves an analog system matrix representative of Kirchhoff s Laws at each simulation step. Each element in an analog design can have an instantaneous influence on any other element in the matrix and vice versa. As such, analog simulation typically is more complex and requires matrix based computation of complex mathematical equations and therefore takes more time than digital simulation.
In the course of developing a circuit design, a designer may decide to replace a given digital version of a design block in the design with an analog version of the design block. One typical reason for replacement of a digital design block with an analog design block is to achieve more accurate simulation results. For example, a digital design block may model a circuit component at a more abstract level that provides less detail concerning the actual structure and behavior of the circuit design than does its analog counterpart. Accordingly, analog simulation using the analog design block often will provide more precise and accurate results. During full chip simulation and verification it is often a design choice as to whether to change some design blocks of the design from digital to analog so as to simulate the circuit with more accuracy to ensure better yield during subsequent manufacture of the physical circuit or to improve performance.
An important consideration in IC design is conserving power in the manufactured IC. A system may use more than one power supply voltage and may use more than one technique for power optimization. A power intent specification for an electronic circuit design is typically provided in text form and the format of a power intent specification ordinarily complies with a well recognized power intent specification format, such as the Common Power Format (CPF) or the Unified Power Format (UPF, e.g., both the Accellera UPF1.0 and IEEE 1801 aka UPF2.0) standards, for example. In general, a power intent specification is captured in a file that is associated with a schematic or block level design, which may be created using schematic capture tools, for example. Defining power intent in a separate file permits the power intent to be readily extracted from the circuit design for exporting to a user or to different processes that execute on a computer system during different stages of the overall IC design process. This allows power intent to be transferred to and incorporated into different stages of electronic design automation (EDA) flow so as to maintain continuity of power intent throughout multiple stages in the design of an IC.
A power intent specification typically is provided in a file format that is accessible by a digital simulation tool. In the past, common practice in mixed-signal simulation and verification methodology was to create a detailed design plan and goals for the digital design blocks of a circuit design and to then approximate the analog functionalities of the design by assuming simple discrete-value models of the analog blocks. Under that approach, only digital simulation was required, and low power intent expressed in a power intent specification file, therefore, could be readily used for an entire chip level simulation and verification. However, more recently, increased design complexity such as multiple feedback paths and interactions between analog and digital design blocks has required use of both digital simulation and analog simulation to accurately simulate and verify such integrated circuit systems. As explained above, this has resulted in designers changing between digital and analog versions of design blocks in the course of different simulation runs.
Various approaches have been proposed previously to apply a power intent specification associated with one or more digital simulation tools to an analog design block. A first prior approach, for example, is to use a corresponding digital design block (such as verilog/VHDL) to approximate analog functionality and to then apply the power intent specification (e.g., CPF) to the digital design block. A limitation to this first approach, explained above, is that using a digital block to approximate analog functionality will sacrifice significant accuracy in simulation and verification. In some of cases, the analog functionality cannot be represented easily by a digital design block, especially if analog behavior is a key function of the overall design. A second prior approach, for example, is to create a digital power supply signal in a digital block and then to use a connect module (CM), which typically is automatically inserted, to convert the power supply for use by an analog design block. There are several shortcomings to this second approach. For instance, a digital or system level designer typically would have to consider the power network for an analog design block at a very early stage of the design flow such as behavior level simulation. Also, additional coding may be required. Moreover, CM techniques typically do not directly support dynamic power supply in simulation. A third prior approach, for example, is to manually create an analog power source according to low power intent expressed in a low power specification file formatted for use by a digital simulator, and to then connect the power source to an analog design block to cause it to adhere to the low power intent. A limitation to this third approach is that in most cases, it is not practical to ask a digital or system level designer to create an analog power source for each analog design block that may have a dynamically changing power supply during simulation.